Baum

A model-based power analysis tool that auto-generates power models from RTL, cell libraries, gate-level netlists and VCD activity vectors — claimed roughly 100x faster than competing approaches while retaining gate-level accuracy, with a full flow that can run within a day.

• Models can be pre-built or generated on the fly, with emulation integration claiming up to 1000x acceleration
• Dynamic power waveform analysis across billions of clock cycles — for power debug, RTL optimization and pre-tapeout signoff

Baum's gate-level power analysis engine, which consumes RTL vectors (e.g. VCD) directly without a separate gate-level simulation run. Offers zero-delay and real-delay conversion modes — the latter carrying glitch-toggle data for gate-level power and timing debug — claimed accurate to within 1–3% of golden reference.

Computes clock-gating metrics (CGR, CGE, ICGE) without a full power run, with automatic ICG extraction straight from RTL and a vectorless mode for designs without a testbench. Produces power-proxy waveforms — including an Active Clock Ratio waveform — that track closely with the gate-level power profile, helping pinpoint peak-power windows.

An AI-generated, low-latency on-chip power meter IP, deliverable as a netlist or hardened block. Claimed roughly 10-cycle latency and ~7k gate overhead independent of design size, with 10–15% error versus gate-level analysis — built for real-time power/thermal management and fine-grained in-silicon debug under real workloads.

Exposes Baum's power analysis and optimization workflows to AI agents via Model Context Protocol — LLM-agnostic and usable by any MCP-enabled agent with no custom integration, claimed to support billion-cycle workloads on large-scale SoC designs.