Jedat (SX-Meister)

A GDS-driven parasitic extraction and analysis solution with built-in device/net and parasitic resistance extraction — no separate LVS/RC tool required — producing color-mapped resistance, voltage and power-density distributions.

• DC/DC sweep analysis: On-resistance, VOH/VOL, IOH/IOL and current-constriction detection
• Resistance distribution analysis with multi-start-point and point-to-point verification
• Power MOS transient analysis: detects delay, imbalance and abnormal voltage fluctuation
• Static thermal analysis showing heat generation and temperature distribution

An integrated schematic-entry platform for LSI and FPD, with parametric 2D array editing for large-scale pixel circuits and automatic feedback of simulation results and layout parasitics into the schematic. Supports EDIF, SPICE netlist and Verilog-HDL.

Simulation waveform analysis claiming gigabyte-scale datasets processed within a minute, with drag-and-drop operation, multi-tab analysis, jitter analysis, histograms, eye diagrams and AD/DA conversion.

An advanced layout editor built for large-scale data (Stream files up to 100GB, 10M+ nets), with polygon/net-driven editing, a Push Aside auto-routing function that eliminates loops, and constraint-driven editing that preserves circuit constraints.