One-time programmable
PermSRAM™ (OTP)
A non-volatile memory macro using standard CMOS processes with no extra mask.
- Proven technology up to 40nm
- Flexible macro sizing from 64bit to 1Mbit
- Partnerships with TSMC, IBM and UMC
Semiconductor IP
NSCore
PermSRAM and TwinBit: non-volatile memory with no extra mask
NSCore non-volatile memory macros use standard CMOS processes without any additional mask, substantially reducing adoption cost. PermSRAM (OTP) is proven to 40nm, with macro capacity ranging from 64bit to 1Mbit.
Products & capabilities
NSCore portfolio
Multi-time programmable
TwinBit™ (MTP)
A multi-time programmable non-volatile macro across mainstream process and voltage combinations.
- TSMC 180: 5.0V, 3.3V, BCD 5V
- TSMC 110LP: 3.3V
- TSMC 55HV: 5V
- UMC 55DDC: 3.3V, 8Mb density
Want to know more about NSCore?
We can arrange a vendor technical briefing, an evaluation licence and a deployment plan to get your team productive quickly.